Training

Getting trained on tool. Expand the relevant tool section below:

Elionix

• You must be at least a Master student or signed up for a long term (>6 months) project to be allowed to use a tool.
• You'll need 3 sessions of about 2.5 hrs each on the tool to get trained on this tool.
  • Session 1 involves exposing alignment marks and one half of the overlay test pattern on a blank chip
  • Session 2 involves using the exposed alignment marks for marker registration and exposing the 2nd pattern (e.g., 2nd half of the overlay pattern).
  • Session 3 involves exposing a "real" pattern on a "real" chip.
• You'll also need a software session of about 0.5 hrs.
• Before any training slots are booked on the tool you'll need all of the following to prepared:
  • Si chip (5-10 mm square) spin coated with A2 and baked at 185C/2mins. This chip will be used for sessions 1 & 2. This has to be a dummy chip.
  • A chip for your 3rd session. This is a "real" chip. Plan this internally within your sub group.
  • A design (gds, dxf, cif) for sessions 1 & 2 with:
    • 4 alignment crosses (find out what marks work on the tool from your sub-group).
    • Something to break the symmetry so you can tell chip orientation with your bare eye
    • A pattern that you will use to test overlay (alignment between two lithography steps). A Vernier pattern is commonly used. Feel free to test your ideas.
    • Something creative, somethin fun :) This is an exercise in learning CAD as well.
  • A design for the "real" chip to be exposed in session 3.
  • Then follow workflow 3 at Qdev wiki to convert your design files into the Elionix exposure format *co7. Make dedicated folders for each exposure.

Heidelberg upg501

• Item 1
• Item 2
  • Sub item 1
  • Sub item 2

Raith e-Line

AJA metallization, sputtering or ion milling

ALD 1 & 2