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updated Elionix training prep instructions
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== Elionix 7000 (100 kV) ==
== Elionix 7000 (100 kV) ==
* You must be at least a Master student or signed up for a long term (>6 months) project to be allowed to use a tool.
* You must be at least a Master student or signed up for a long term (>6 months) project to be allowed to use the tool.
* Elionix is a high level tool: Make sure you are already trained to:
* Elionix is a high level tool. Make sure you are already trained to:
** enter the cleanroom
** enter the cleanroom;
** use the microscope, spinner, asher
** use the microscope, spinner, asher;
** any other tool you'll need to prepare chips for the training. This could be the micromanipulator or the Heidelberg.
** use any other tool you might need to prepare chips for the training. This could be the micromanipulator or the Heidelberg.
* You'll need 3 sessions of about 2.5 hrs each on the tool to get trained on this tool.
* You'll need 1+3 sessions of about 2.5 hrs each on the tool to get trained on this tool.
** Session 1 involves exposing alignment marks and one half of the overlay test pattern on a blank chip. After exposure you need to develop the pattern in the PMMA developer. This is enough for session 2.
** Session 0 teaches you how to load/unload the sample and how to condition the beam.
** Session 2 involves using the exposed alignment marks for marker registration and exposing the 2nd pattern (e.g., 2nd half of the overlay pattern).
** Session 1 involves exposing alignment marks and one half of the overlay test pattern on a blank chip. After exposure you need to develop the pattern in PMMA developer. Once you can determine the relative position of the lower left alignment mark with respect to the lower left chip corner, you are ready for session 2.
** Session 3 involves exposing a "real" pattern on a "real" chip.
** Session 2 involves using the exposed alignment marks for marker registration and exposing the 2nd pattern (i.e. the 2nd half of the overlay pattern).
** Session 3 involves exposing a "real" pattern on a "real" chip on your own.
* Before any training slots are booked on the tool you'll need all of the following prepared:
* Before any training slots are booked on the tool you'll need all of the following prepared:
** Shadow someone on the tool 2-3 times before starting the prep.
** Shadow someone on the tool 2-3 times before starting the prep.
** Si chip (5-10 mm square) spin coated with A4.5 and baked at 185C/2mins. This chip will be used for sessions  1 & 2. This has to be a dummy chip.
** Si chip (5-20 mm square) spin coated with A4.5 and baked at 185C/2mins. This chip will be used for sessions  1 & 2. This has to be a dummy chip.
** A chip for your 3rd session. This is a "real" chip. Plan this internally within your sub group.
** A chip for your 3rd session. This is a "real" chip. Plan this internally within your sub group.
** A design (gds, dxf, cif) for sessions 1 & 2 with:
** A design (GDS is preferred, DXF ''might'' work) for sessions 1 & 2 with:
*** 4 alignment crosses (find out what marks work on the tool from your sub-group).
*** 4 alignment crosses (find out what marks work on the tool from your sub-group). The crosses should be a few millimeters apart. Make sure each cross is within one writefield when converting the design in WeCaS.
*** Something to break the symmetry so you can tell chip orientation with your bare eye
*** Something to break the symmetry so you can tell chip orientation with your bare eye after the 1st exposure.
*** A pattern that you will use to test overlay (alignment between two lithography steps). A Vernier pattern is commonly used. Feel free to test your ideas.
*** A pattern that you will use to test overlay quality (alignment precision between two lithography steps). A Vernier pattern is commonly used. Feel free to test your ideas.
*** Something creative, somethin fun :) This is an exercise in learning CAD as well.
*** Something creative, something fun :) This is an exercise in learning CAD as well.
** A design for the "real" chip to be exposed in session 3.
** A design for the "real" chip to be exposed in session 3.
* You'll also need a software session of about 0.5 hrs -- arrange this with an Elionix superuser within your group.
* You'll also need a software session of about 0.5 hrs -- arrange this with an Elionix superuser within your group.
* Then follow workflow 3 at [https://wiki.nbi.ku.dk/qdevwiki/ElionixCheatSheet Qdev wiki] to convert your design files into the Elionix exposure format .co7. Make dedicated folders for each exposure.
* Then follow workflow 3 at [https://wiki.nbi.ku.dk/qdevwiki/ElionixCheatSheet Qdev wiki] to convert your design files into the Elionix exposure format .co7. Make dedicated folders for each exposure. '''Contact the cleanroom staff when you are ready with this step.'''
* Note: Do not use Beamer to prep the Elionix con files
* Note: Do not use Beamer to prep the Elionix con files.


== Elionix F-125 (125 kV) ==
== Elionix F-125 (125 kV) ==
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== AJA metallization, sputtering or ion milling ==
== AJA metallization, sputtering or ion milling ==
* You must have a sample ready before the training is arranged.
* You must have a sample ready before the training is arranged.
* Shadow someone 2-3 times before contacting the staff.


== ALD 1 & 2 ==
== ALD 1 & 2 ==

Revision as of 14:10, 15 July 2019

Getting trained on a tool. Refer to the relevant tool section.

Elionix 7000 (100 kV)

  • You must be at least a Master student or signed up for a long term (>6 months) project to be allowed to use the tool.
  • Elionix is a high level tool. Make sure you are already trained to:
    • enter the cleanroom;
    • use the microscope, spinner, asher;
    • use any other tool you might need to prepare chips for the training. This could be the micromanipulator or the Heidelberg.
  • You'll need 1+3 sessions of about 2.5 hrs each on the tool to get trained on this tool.
    • Session 0 teaches you how to load/unload the sample and how to condition the beam.
    • Session 1 involves exposing alignment marks and one half of the overlay test pattern on a blank chip. After exposure you need to develop the pattern in PMMA developer. Once you can determine the relative position of the lower left alignment mark with respect to the lower left chip corner, you are ready for session 2.
    • Session 2 involves using the exposed alignment marks for marker registration and exposing the 2nd pattern (i.e. the 2nd half of the overlay pattern).
    • Session 3 involves exposing a "real" pattern on a "real" chip on your own.
  • Before any training slots are booked on the tool you'll need all of the following prepared:
    • Shadow someone on the tool 2-3 times before starting the prep.
    • Si chip (5-20 mm square) spin coated with A4.5 and baked at 185C/2mins. This chip will be used for sessions 1 & 2. This has to be a dummy chip.
    • A chip for your 3rd session. This is a "real" chip. Plan this internally within your sub group.
    • A design (GDS is preferred, DXF might work) for sessions 1 & 2 with:
      • 4 alignment crosses (find out what marks work on the tool from your sub-group). The crosses should be a few millimeters apart. Make sure each cross is within one writefield when converting the design in WeCaS.
      • Something to break the symmetry so you can tell chip orientation with your bare eye after the 1st exposure.
      • A pattern that you will use to test overlay quality (alignment precision between two lithography steps). A Vernier pattern is commonly used. Feel free to test your ideas.
      • Something creative, something fun :) This is an exercise in learning CAD as well.
    • A design for the "real" chip to be exposed in session 3.
  • You'll also need a software session of about 0.5 hrs -- arrange this with an Elionix superuser within your group.
  • Then follow workflow 3 at Qdev wiki to convert your design files into the Elionix exposure format .co7. Make dedicated folders for each exposure. Contact the cleanroom staff when you are ready with this step.
  • Note: Do not use Beamer to prep the Elionix con files.

Elionix F-125 (125 kV)

Please contact Zhe Liu (zhe.liu@nbi.ku.dk)

Heidelberg upg501

  • Have a design file ready. GDS, DXF or CIF format works fine. Make sure you are familiar with the design before your actual session.
  • Have a chip spin coated with an appropriate photoresist before the training session.
    • The photoresist is sensitive to white light. Use the yellow filter on the microscopes. The light source in the both scribers is white and will already "expose" your resist.

Raith e-Line

  • A design (gds, dxf, cif) for sessions 1 & 2 with:
    • 4 alignment crosses (find out what marks work on the tool from your sub-group).
    • Something to break the symmetry so you can tell chip orientation with your bare eye.
    • A pattern that you will use to test overlay (alignment between two lithography steps). A Vernier pattern is commonly used. Feel free to test your ideas.
    • Something creative, somethin fun :) This is an exercise in learning CAD as well.

JEOL 7800-F

  • Training takes about 2-3 sessions.
  • You need a chip/sample to be imaged before a session is booked.
  • Be familiar with the materials on the sample to be imaged and what feature is it that is of critical interest -- something that makes or breaks your device.
  • Request the training session only once you have gathered the chips and information.

AJA metallization, sputtering or ion milling

  • You must have a sample ready before the training is arranged.
  • Shadow someone 2-3 times before contacting the staff.

ALD 1 & 2

  • You must have a sample ready before the training is arranged.

F&S autobonder

  • You must have a chip for bonding.
  • Figure out which daughterboard is it that your team/fridge needs.
  • Have a team member show your how to glue the chip to the daughterboard with silver paint, PMMA or whatever is specific to your measurement.
  • Request to a training session at this point.