* You must have a sample for bonding ready before the training is arranged.
* Figure out which daughterboard is it that your team/fridge needs.
* Have a team member show your how to glue the chip to the daughterboard with silver paint, pmma or whatever is specific to your measurement.
* Request to a training session at this point.
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Revision as of 10:27, 5 November 2018
Getting trained on tool. Expand the relevant tool section below:
Elionix 7000 (100 kV)
You must be at least a Master student or signed up for a long term (>6 months) project to be allowed to use a tool.
Elionix is a high level tool: Make sure you are already trained to:
enter the cleanroom
use the microscope, spinner, asher
any other tool you'll need to prepare chips for the training. This could be the micromanipulator or the Heidelberg.
You'll need 3 sessions of about 2.5 hrs each on the tool to get trained on this tool.
Session 1 involves exposing alignment marks and one half of the overlay test pattern on a blank chip. After exposure you need to develop the pattern in the PMMA developer. This is enough for session 2.
Session 2 involves using the exposed alignment marks for marker registration and exposing the 2nd pattern (e.g., 2nd half of the overlay pattern).
Session 3 involves exposing a "real" pattern on a "real" chip.
Before any training slots are booked on the tool you'll need all of the following prepared:
Si chip (5-10 mm square) spin coated with A2 and baked at 185C/2mins. This chip will be used for sessions 1 & 2. This has to be a dummy chip.
A chip for your 3rd session. This is a "real" chip. Plan this internally within your sub group.
A design (gds, dxf, cif) for sessions 1 & 2 with:
4 alignment crosses (find out what marks work on the tool from your sub-group).
Something to break the symmetry so you can tell chip orientation with your bare eye
A pattern that you will use to test overlay (alignment between two lithography steps). A Vernier pattern is commonly used. Feel free to test your ideas.
Something creative, somethin fun :) This is an exercise in learning CAD as well.
A design for the "real" chip to be exposed in session 3.
You'll also need a software session of about 0.5 hrs - arrange this with an Elionix superuser within your group.
Then follow workflow 3 at Qdev wiki to convert your design files into the Elionix exposure format *co7. Make dedicated folders for each exposure.
Note: Do not use Beamer to prep the Elionix con files
Elionix F-125 (125 kV)
Please contact Zhe Liu (zhe.liu [a] nbi ku dk)
Heidelberg upg501
Have a design file ready. GDS, DXF or CIF format works fine. Make sure you are familiar with the design before your actual session.
Have a chip spin coated with an appropriate photoresist before the training session.
The photoresist is sensitive to white light. Use the yellow filter on the microscopes. The light source in the both scribers is white and will already "expose" your resist.
Raith e-Line
A design (gds, dxf, cif) for sessions 1 & 2 with:
4 alignment crosses (find out what marks work on the tool from your sub-group).
Something to break the symmetry so you can tell chip orientation with your bare eye
A pattern that you will use to test overlay (alignment between two lithography steps). A Vernier pattern is commonly used. Feel free to test your ideas.
Something creative, somethin fun :) This is an exercise in learning CAD as well.
AJA metallization, sputtering or ion milling
You must have a sample ready before the training is arranged.
ALD 1 & 2
You must have a sample ready before the training is arranged.
F&S autobonder
You must have a sample for bonding ready before the training is arranged.
Figure out which daughterboard is it that your team/fridge needs.
Have a team member show your how to glue the chip to the daughterboard with silver paint, pmma or whatever is specific to your measurement.