Design template for lithography training: Difference between revisions
Jump to navigation
Jump to search
| Line 20: | Line 20: | ||
* Include at least 4 alignment marks, each at the corner of your chip | * Include at least 4 alignment marks, each at the corner of your chip | ||
* Include a vernier pattern to test the alignment accuracy of the tool | * Include a vernier pattern to test the alignment accuracy of the tool. | ||
* The design should be in gds or dxf format | * The design should be in gds or dxf format | ||
* Your design will have two layers: one for session 2 and one for | * Your design will have two layers: one for session 2 and one for ''Session 3'' | ||
* Contain your design in an area of 600x1200 μm2 | * Contain your design in an area of 600x1200 μm2 | ||
* Lines can have a width of a minimum | * Avoid placing your design in the centre of the chip (ie break the symmetry). This will make it easier for you to identify the correct orientation when loading ''Session 3'' | ||
* Lines can have a width of a minimum 60 nm up to 2 μm | |||
* The complete exposure shouldn't take more than 90 mins | * The complete exposure shouldn't take more than 90 mins | ||
* Most importantly, let your creativity be free. You can use images transformed in gds. | * Most importantly, let your creativity be free. You can use images transformed in gds. | ||
Latest revision as of 13:42, 18 February 2026
Introduction
We recommend using a combination of the following tools for designing devices:
- Klayout or CleWin (only for Windows)
- Phidl (python-based)
- Copilot (great tool to boost your productivity)
There is a code you can use as a basis to build the design for your EBL trainings.
You can find them on N/SCI-NBI-Cleanroom/Elionix100 EXP files/general Training.
- CR_template_training.gds design with alrignment marks and vernier patterns (~27mins exposure time)
- design_template.ipynb
- layer1_training.ftxt BEAMER file for elionix 100keV with 500pA
Design requirements
The chips provided from the cleanroom are usually 10x10mm2, so the design should be inside this area You are welcome to use the provided code and explore different possibilities on your own.
As a baseline, please follow the guidelines:
- Include at least 4 alignment marks, each at the corner of your chip
- Include a vernier pattern to test the alignment accuracy of the tool.
- The design should be in gds or dxf format
- Your design will have two layers: one for session 2 and one for Session 3
- Contain your design in an area of 600x1200 μm2
- Avoid placing your design in the centre of the chip (ie break the symmetry). This will make it easier for you to identify the correct orientation when loading Session 3
- Lines can have a width of a minimum 60 nm up to 2 μm
- The complete exposure shouldn't take more than 90 mins
- Most importantly, let your creativity be free. You can use images transformed in gds.